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Vivado Turtorial 01 —— 使用vivado中debug功能(类似ISE中ChipScope)

2016-06-16

1.基于BASYS3板子,有如下代码:

module top(
    input        clk,
    input        rst,
    output       test_clk   
    );

parameter DIV_CNT = 2;

reg clk25M;
reg [31:0] cnt = 0;
always@(posedge clk)begin
    if (cnt==DIV_CNT-1)
        begin
            clk25M <= ~clk25M;
            cnt <= 0;
        end
    else
        begin
            cnt <= cnt + 1'b1;
        end
end
assign  test_clk = rst ? 1'b0 : clk25M;

管脚配置XDC文件内容如下:

set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property PACKAGE_PIN V17 [get_ports rst]
set_property IOSTANDARD LVCMOS33 [get_ports rst]
set_property PACKAGE_PIN L1 [get_ports test_clk]
set_property IOSTANDARD LVCMOS33 [get_ports test_clk]

2.占击左侧Run Synthesis,综合

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3.完成之后,再点击 Open Synthesized Design,打开之后,点Tools下的Set Up Debug…

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如下

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4.选择Find Nets to Add…

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5.点OK

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6.选中想要观察的信号,点OK

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7.出现红色,在红色地方右键。

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8.选择Select Clock Domain Picture

9.选择ALL_CLOCK,然后选择clk_IBUF或clk_IBUF_BUFG

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10.选择合适的采集深度,1024通常够用

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11.Finish

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12.点击左侧的Generate Bitstream

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13.完成后,点Open Hardware Manager

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14.将板子连接到电脑上,然后Open Target -> Auto Connect

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15.在xc7a35t上面,右键->Program Device…

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16.Program

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17.点击Trigger

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18.会自动弹出波形

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19.此时,只有test_clk信号,没有rst信号。在Debug Probes区域中,rst_IBUF上右键

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20.Add Probes to Wave Form

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21.即可看到rst也在波形中了,添加其它信号类似

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22.鼠标点住rst_IBUF,拖拽到图中区域放开鼠标

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23.rst_IBUF信号会出现在框中

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24.点开Compare Value下拉菜单,设置如下,点击OK

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25.把BASYS3板子上的SW0,拔到上面。点击Run Trigger按钮

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26.注意到这里应该显示Wait…

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27.此时,在板子上,把SW0拔下来。注意到,这里会一闪而过Full,然后又显示Idle。如果没观察到,可以从25步骤再重来

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28.再打开波形,如下图

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29.回到这个界面,将Trigger Position 设置为500。再重复24-28步骤。然后再观察波形中,第500个周期,波形前后数据的变化

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